为什么处理器越快，「内存墙」问题反而越突出？
Why does the memory wall become a worse bottleneck as processors get faster?
多年来处理器的运算吞吐以远高于 DRAM 访问延迟改善的速度增长，两者差距不断扩大，使越来越多程序时间耗在等待内存返回数据上。这一现象被称为内存墙：即使算术单元再快，一次缓存缺失动辄要等上百个时钟周期，整体性能仍被访存拖住。工程上的应对是加深缓存层次、提高内存级并行（允许多个未完成访存同时进行）、硬件预取，以及把计算搬到数据附近，而不是单纯提高主频。
For decades CPU arithmetic throughput improved far faster than DRAM latency, so the gap widened until many programs spend most of their time waiting on memory rather than computing. This is the memory wall: however fast the ALUs get, a cache miss costing hundreds of cycles still dominates runtime. Mitigations are deeper cache hierarchies, more memory-level parallelism (many outstanding misses in flight), hardware prefetching and moving computation closer to the data — not simply raising clock frequency.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-11-04
来源 · Source
Wulf, McKee,《Hitting the memory wall》,ACM SIGARCH Computer Architecture News,1995 (DOI: 10.1145/216585.216588)
Wulf and McKee, 'Hitting the memory wall', ACM SIGARCH Computer Architecture News, 1995, DOI: 10.1145/216585.216588
独立核验依据 · Independent verification: 核验依据 1 Crossref DOI 10.1145/216585.216588
#内存墙 #缓存缺失 #访存延迟 #体系结构
超标量和乱序执行有什么区别？
What is the difference between superscalar and out-of-order execution?
超标量指 CPU 每个时钟周期能同时发射多条指令到多个执行单元，从而提高并行度。乱序执行则允许在不破坏数据依赖的前提下，把后面不依赖前面结果的指令提前执行，以填满闲置的执行单元。二者常结合使用：超标量提供硬件并行，乱序执行优化指令调度。
Superscalar means a CPU can issue multiple instructions per clock cycle to several execution units, increasing parallelism. Out-of-order execution lets instructions whose results are not needed by earlier ones run ahead of schedule, keeping idle units busy without violating dependencies. They are often combined: superscalar provides hardware parallelism and out-of-order execution optimizes scheduling.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#超标量 #乱序执行 #CPU
CPU 的指令流水线是怎么提升性能的？
How does a CPU instruction pipeline improve performance?
一条指令的执行可以拆成取指、译码、执行、写回等阶段，流水线让不同指令的阶段重叠进行，就像工厂流水线，吞吐量理论上提高到阶段数倍。但它带来冒险问题：相邻指令可能争用同一数据（数据冒险）或改变跳转（控制冒险），需要转发、乱序执行和分支预测来解决。超标量设计还能同时发射多条指令。
Executing an instruction splits into stages like fetch, decode, execute, and write-back. Pipelining overlaps these stages across different instructions—like a factory line—boosting throughput up to the number of stages in theory. Hazards arise though: neighboring instructions may race on data (data hazards) or alter control flow (control hazards), handled by forwarding, out-of-order execution, and branch prediction. Superscalar designs even issue several instructions at once.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#流水线 #冒险 #分支预测
NUMA 架构解决了多处理器系统的什么问题？
What problem does NUMA architecture solve in multiprocessor systems?
在多个 CPU 插槽的大型系统中，内存离不同处理器距离不同，统一访问会变慢。NUMA（非统一内存访问）把内存就近分给各处理器节点，访问本地内存更快、跨节点更慢。操作系统据此把进程和内存尽量放在同一节点，以减少远程访问开销。
In large multi-socket systems, memory sits at different distances from processors, and uniform access becomes slow. NUMA (non-uniform memory access) assigns memory local to each processor node, making local access faster and cross-node access slower. The OS then tries to keep a process and its memory on the same node to cut remote-access cost.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#NUMA #多处理器 #内存
2005 年之后 CPU 主频为什么基本停在 3–5 GHz 不再猛涨？
Why have CPU clock speeds stalled around 3–5 GHz since roughly 2005?
登纳德缩放定律曾保证晶体管变小时电压同步下降、功率密度不变，于是主频能随工艺节点免费上涨；进入 90 纳米以后阈值电压难以再降、漏电流显著增大，这条规律失效。此后继续拉高频率会让芯片功率与发热按超线性增长，撞上功耗墙，散热与供电成为硬约束。业界因此转向多核、异构加速器和专用单元，用并行度而不是吉赫兹换性能。
Dennard scaling once let supply voltage fall in step with transistor size so power density stayed flat and clock speed rose for free at each process node. Below roughly 90 nm threshold voltages stopped shrinking and leakage current grew, breaking that relationship. Pushing frequency further makes power and heat grow superlinearly — the power wall — so cooling and power delivery became hard limits, and vendors switched to multicore designs, heterogeneous accelerators and domain-specific units, buying performance with parallelism instead of gigahertz.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-10-03 · 2 条独立证据
来源 · Source
Hennessy 与 Patterson《Computer Architecture: A Quantitative Approach》(第 6 版) 第 1 章
Hennessy & Patterson, "Computer Architecture: A Quantitative Approach" (6th ed.), ch. 1
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL17914655W：Computer architecture
#登纳德缩放 #功耗墙 #多核 #主频
分支预测为什么重要，它是如何工作的？
Why is branch prediction important and how does it work?
现代 CPU 大量使用流水线，遇到 if 等条件分支时若等结果出来再取下一指令会浪费大量周期，分支预测便提前猜测走向。预测正确时流水线顺畅，错误时则要清空并重取，代价很高。处理器常用两位饱和计数器等历史统计方法来提高猜测准确率。
Modern CPUs rely heavily on pipelines; when they hit a conditional branch such as an if, waiting for the outcome before fetching the next instruction wastes many cycles, so branch prediction guesses the direction in advance. A correct guess keeps the pipeline flowing, while a misprediction requires flushing and refetching at high cost. Processors often use history statistics such as two-bit saturating counters to improve accuracy.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#分支预测 #流水线 #CPU
什么是内存地址空间，物理地址和虚拟地址有何不同？
What is a memory address space, and how do physical and virtual addresses differ?
地址空间是所有可被寻址位置的总称。物理地址是内存芯片上真实存在的编号，虚拟地址是程序看到的逻辑编号。通过页表，操作系统把虚拟地址映射到物理地址，使程序无需关心实际内存布局，也便于实现隔离和保护。
An address space is the full set of addressable locations. A physical address is the real number on the memory chips, while a virtual address is the logical number a program sees. Through page tables, the OS maps virtual to physical addresses so programs need not know the real memory layout and isolation and protection are easier to enforce.
难度 专业 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#地址空间 #虚拟地址 #物理地址
光线与百万级三角形逐个求交太慢，加速结构（如 BVH）是怎么提速的？
Testing rays against millions of triangles is slow — how do acceleration structures like BVH speed it up?
层次包围盒（BVH）把场景组织成一棵树：每个内部节点存包围盒，叶子存若干三角形。求交时先测光线与包围盒，不相交就剪掉整棵子树，相交才递归进入，理想情况下每次求交只访问 O(log n) 个节点。GPU 上的 RT core 硬件加速、表面积启发式（SAH）分割，以及 BVH/KD-tree 等结构共同支撑起实时光线追踪。
A bounding volume hierarchy organizes the scene as a tree: internal nodes store bounding boxes and leaves hold small sets of triangles. A ray is first tested against the box; a miss prunes the whole subtree, and a hit recurses, so ideally each intersection visit costs only O(log n) nodes. Dedicated RT cores on GPUs, surface-area-heuristic (SAH) partitioning, and structures like BVH/KD-tree together enable real-time ray tracing.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-11-03
来源 · Source
Akenine-Moller、Haines 与 Hoffman,《Real-Time Rendering》第4版,CRC Press,2018
T. Akenine-Moller et al., Real-Time Rendering, 4th ed., CRC Press, 2018
独立核验依据 · Independent verification: 核验依据 1 OPENLIBRARY 标识 /works/OL17682001W：Real-time rendering（首版
#BVH #光线追踪 #加速结构
DMA（直接内存访问）解决了什么问题？
What problem does DMA (direct memory access) solve?
如果没有 DMA，外设与内存之间传输数据都要经过 CPU 逐字节搬运，会大量占用 CPU 时间。DMA 控制器可以在 CPU 不插手的情况下，直接在外设和内存间搬运大块数据，完成后用中断通知 CPU。这样 CPU 在传输期间可去处理别的任务。
Without DMA, moving data between a peripheral and memory would force the CPU to copy it byte by byte, hogging its time. A DMA controller can transfer large blocks directly between peripheral and memory without CPU involvement, then signal the CPU with an interrupt when done. This frees the CPU to do other work during the transfer.
难度 专业 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#DMA #外设 #总线
多核处理器之间如何保持缓存数据一致（以 MESI 为例）？
How do multi-core processors keep cache data consistent, using MESI as an example?
在多核系统中，每个核心可能缓存同一内存块的副本，MESI 协议用 Modified、Exclusive、Shared、Invalid 四种状态跟踪这些副本。当某核心改写数据时，协议会让其他核心的对应副本失效或更新，从而保证它们看到一致的值。这类协议通过核间总线广播和监听来实现。
In multi-core systems each core may cache a copy of the same memory block; the MESI protocol tracks these copies with four states: Modified, Exclusive, Shared, and Invalid. When one core writes data, the protocol invalidates or updates the corresponding copies in other cores so they all observe a consistent value. Such protocols work by broadcasting and snooping on the inter-core bus.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#缓存一致性 #MESI #多核
什么是缓存行（cache line）和局部性原理？
What are cache lines and the principle of locality?
缓存不是逐字节传送，而是以“缓存行”（通常 64 字节）为单位成块搬移。局部性原理指程序倾向重复访问近期用过的数据（时间局部性）和相邻的数据（空间局部性）。利用好局部性，一次载入的整行能被多次命中，显著提升效率。
Cache does not move data byte by byte but in blocks called cache lines, typically 64 bytes. The principle of locality says programs tend to reuse recent data (temporal locality) and nearby data (spatial locality). By exploiting locality, one loaded line gets hit many times, markedly improving efficiency.
难度 专业 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#缓存行 #局部性 #缓存
什么是大端序和小端序（字节序）？
What are big-endian and little-endian byte orders?
当多字节数据（如一个 32 位整数）存入内存时，字节排列顺序有约定：大端序把最高有效字节放在最低地址，小端序则把最低有效字节放在最低地址。x86 等常用小端序，网络协议常规定用大端序。不同端序的系统直接交换二进制数据时必须做转换。
When a multi-byte value such as a 32-bit integer is stored, the byte arrangement varies: big-endian puts the most significant byte at the lowest address, while little-endian puts the least significant byte there. x86 and others commonly use little-endian, whereas network protocols often mandate big-endian. Systems with different byte orders must convert when exchanging raw binary data.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#字节序 #大端 #小端
在内存里直接计算，为什么能省电？
Why does computing inside memory save power?
传统架构要把数据从内存搬到 CPU 再算，来回搬运消耗大量能量；存算一体让运算直接在存储阵列附近发生，省掉了频繁搬运，因此特别适合低功耗的 AI 推理。
Classic architectures haul data from memory to the CPU and back, burning energy in movement; in-memory computing does the math right where data sits, skipping the transfers—great for low-power AI inference.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#存算一体 #省电
为什么说计算机采用“存储层次结构”？
Why do computers use a memory hierarchy?
存储层次结构按照速度、容量、成本把寄存器、缓存、内存、硬盘等组织成金字塔：越往上越快越贵容量越小，越往下越慢越便宜容量越大。程序运行时把最频繁访问的数据放在上层，从而在成本和性能间取得平衡。这种分层利用了“局部性”原理，即程序常反复访问相近的数据。
The memory hierarchy organizes registers, caches, RAM, and disks into a pyramid by speed, capacity, and cost: higher levels are faster, pricier, and smaller, while lower levels are slower, cheaper, and larger. The most frequently used data is kept in upper levels to balance cost and performance. This layering exploits locality, the tendency of programs to repeatedly access nearby data.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#存储层次 #缓存 #局部性
CPU 执行一条指令通常经历哪些阶段？
What stages does a CPU typically go through to execute one instruction?
经典流程是“取指—译码—执行”，有的还包含“访存”和“写回”。取指从内存读入指令，译码分析它要做什么、操作数在哪，执行让 ALU 或访存完成运算，结果再写回寄存器或内存。流水线就是把这几个阶段重叠起来做。
The classic flow is fetch, decode, and execute, sometimes extended with memory access and write-back. Fetch reads the instruction from memory, decode figures out what it does and where its operands are, execute lets the ALU or memory perform the operation, and the result is written back to a register or memory. Pipelining overlaps these stages.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#指令周期 #取指 #译码
CPU 缓存有什么作用，为什么需要它？
What is the purpose of CPU cache and why is it needed?
CPU 缓存是位于 CPU 与主存之间的高速小容量存储器，用来暂存最近或即将使用的数据，缓解 CPU 远快于内存的速度差距。当 CPU 需要的数据已在缓存中时称为“命中”，否则需到慢得多的主存去取。多级缓存（L1/L2/L3）按速度与容量逐级权衡来组织。
CPU cache is a small, fast memory between the CPU and main memory that holds recently or soon-to-be-used data, bridging the large speed gap between a fast CPU and slower RAM. When the needed data is already in cache it is a hit; otherwise the CPU must fetch it from much slower main memory. Multi-level caches (L1/L2/L3) trade speed against capacity at each tier.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#缓存 #CPU #存储层次
服务器内存为什么普遍要用 ECC，而普通台式机常常不用？
Why do servers almost always use ECC memory while most desktops skip it?
ECC 内存在每 64 位数据上额外存 8 位校验位，采用 SEC-DED 类汉明码，能自动纠正单比特翻转并检出双比特错误。宇宙射线与电路噪声导致的位翻转按每 GB 每小时算概率很低，但服务器内存容量大、连续运行时间长，累计出错次数不可忽略，一次静默错误就可能污染数据库或长时间计算的结果。消费级机器成本敏感、容错要求低，错误通常表现为可重启恢复的崩溃，所以常省去 ECC。
ECC modules store 8 extra check bits per 64 data bits using a SEC-DED Hamming-style code, so a single flipped bit is corrected transparently and double-bit errors are at least detected. Bit flips from cosmic rays or electrical noise are rare per gigabyte-hour, but servers run huge memories continuously, so the aggregate rate matters and one silent corruption can poison a database or a week-long computation. Desktops are cost-sensitive, tolerate the occasional crash and usually just reboot, so ECC is often omitted.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-10-04
来源 · Source
Hamming《Error Detecting and Error Correcting Codes》(Bell System Technical Journal, 1950)
Hamming, "Error Detecting and Error Correcting Codes," Bell System Technical Journal (1950)
独立核验依据 · Independent verification: 核验依据 1 DOI 10.1002/j.1538-7305.1950.tb00467.x
#ECC内存 #汉明码 #位翻转 #服务器可靠性
哈佛架构与冯·诺依曼架构有何区别？
How does the Harvard architecture differ from the von Neumann architecture?
哈佛架构将指令存储和数据存储分开，使用两条独立的总线，可同时取指令和读写数据，从而提升吞吐。冯·诺依曼架构则让指令和数据共用同一存储和总线，结构更简单。现代处理器常采用“改良哈佛”结构，在高速缓存层级分别存放指令与数据。
The Harvard architecture separates instruction memory from data memory and uses two independent buses, allowing instructions to be fetched while data is read or written, which improves throughput. The von Neumann architecture lets instructions and data share one memory and bus, making it simpler. Many modern processors use a modified Harvard design that keeps instructions and data in separate cache levels.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#哈佛架构 #总线 #计算机组成
计算机为什么用「补码」表示负数，而不是简单加一个符号位？
Why do computers store negative numbers in two's complement instead of just adding a sign bit?
补码把负数 -x 编码成 2^n - x，于是同一套二进制加法电路既能做加法也能做减法：减法就是加上减数的补码，硬件不必为符号单独设计一条通路。原码和反码都会产生 +0 与 -0 两个零，使比较和判零逻辑变复杂，而 n 位补码的零唯一，表示范围是 -2^(n-1) 到 2^(n-1)-1。代价是负数比正数多一个，对最小负数取相反数会溢出。
Two's complement encodes -x as 2^n - x, so a single adder handles both addition and subtraction: subtracting means adding the complement, and no separate sign-handling datapath is needed. Sign-magnitude and one's complement each give two encodings of zero, complicating comparisons and zero tests, whereas two's complement has a unique zero and spans -2^(n-1) through 2^(n-1)-1. The trade-off is one extra negative value, so negating the most negative number overflows.
难度 进阶 · 适合 小学高段(9-12)
CC BY 4.0 · 已核验 · Verified 2026-10-04
来源 · Source
Patterson 与 Hennessy《Computer Organization and Design: The Hardware/Software Interface》(RISC-V 版) 第 2 章
Patterson & Hennessy, "Computer Organization and Design: The Hardware/Software Interface" (RISC-V ed.), ch. 2
独立核验依据 · Independent verification: 核验依据 1 ISBN 9781558604285 (2009)
#补码 #有符号整数 #溢出 #数字逻辑
“并发”和“并行”是一回事吗？
Are concurrency and parallelism the same thing?
不是。并发指多个任务在一段时间内交替推进、看似同时，强调程序结构的组织，单核也能做到。并行指多个任务真正同时执行，需要多核或多机。并发是关于“应对多件事”的设计，并行是关于“同时做多件事”的执行能力。
No. Concurrency means multiple tasks make progress over a period by interleaving, emphasizing how a program is structured, and it works even on a single core. Parallelism means tasks literally execute at the same time, requiring multiple cores or machines. Concurrency is about dealing with many things in design, parallelism about doing many things at once in execution.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#并发 #并行 #多核
存算一体是怎么缓解“内存墙”问题的？
How does in-memory computing ease the 'memory wall'?
“内存墙”指 CPU 算力增长远快于内存带宽，数据喂不过来。存算一体把部分计算下沉到内存内部，减少数据在芯片间的长途搬运，从而缓解带宽瓶颈、提升能效比。
The 'memory wall' is when CPU speed outpaces memory bandwidth and data can't be fed fast enough. Doing computation inside memory cuts long data movement, easing the bandwidth bottleneck and boosting energy efficiency.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#内存墙 #存算
RISC 和 CISC 两种指令集风格有何区别？
What is the difference between RISC and CISC instruction set styles?
CISC（复杂指令集）提供很多功能强大的复杂指令，单条可做较多事，典型如 x86。RISC（精简指令集）只保留简单、长度规整的指令，靠编译器组合实现复杂功能，典型如 ARM、RISC-V，更容易做深流水线和高效率。现代两者界限已模糊，互相借鉴。
CISC (complex instruction set) offers many powerful, complex instructions that each do a lot, as in x86. RISC (reduced instruction set) keeps only simple, uniform-length instructions and relies on the compiler to combine them, as in ARM and RISC-V, which eases deep pipelining and efficiency. Modern designs blur the line and borrow from both.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#RISC #CISC #指令集
什么是指令流水线，它能提升性能吗？
What is an instruction pipeline and does it improve performance?
指令流水线把一条指令的执行拆成取指、译码、执行等多个阶段，让不同指令的不同阶段重叠进行，从而提高单位时间内的吞吐。就像工厂流水线，前一指令在运行时，后一指令已开始取指。当遇到分支跳转或数据依赖时，流水线可能停顿，性能提升会打折扣。
An instruction pipeline splits execution into stages such as fetch, decode, and execute so that different stages of different instructions overlap, raising throughput per unit time. Like a factory assembly line, while one instruction runs, the next is already being fetched. Branches or data dependencies can stall the pipeline, reducing the expected gain.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#流水线 #指令 #CPU
光线追踪为什么能做出逼真的反射和阴影？它与光栅化有什么不同？
Why does ray tracing produce realistic reflections and shadows, and how does it differ from rasterization?
光栅化把三维几何投影到屏幕上，只绘制直接可见的表面，阴影和反射要靠额外技巧（如阴影贴图）；光线追踪从相机向每个像素发射光线，追踪光线在场景中的反弹与求交，能自然得到软阴影、镜面反射和全局光照，效果逼真但计算量大，长期用于电影，近年靠 GPU 硬件加速进入实时渲染领域。
Rasterization projects 3D geometry onto the screen, drawing only directly visible surfaces, so shadows and reflections need extra tricks like shadow mapping. Ray tracing shoots rays from the camera through each pixel and traces their bounces and intersections in the scene, naturally producing soft shadows, specular reflections and global illumination — realistic but expensive; long used in film, it entered real-time rendering thanks to GPU hardware acceleration.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-11-03
来源 · Source
Akenine-Moller、Haines 与 Hoffman,《Real-Time Rendering》第4版,CRC Press,2018
T. Akenine-Moller et al., Real-Time Rendering, 4th ed., CRC Press, 2018
独立核验依据 · Independent verification: 核验依据 1 OPENLIBRARY 标识 /works/OL17682001W：Real-time rendering（首版
#光线追踪 #渲染 #图形学
固态硬盘的“磨损均衡”是怎么回事？
How does wear leveling work in SSDs?
闪存每个存储块有有限的擦写次数，若总改写同一区域会提前损坏。磨损均衡由控制器记录各块擦写次数，把写入尽量均匀分散到全盘，避免个别块早衰。配合垃圾回收，它能显著延长 SSD 寿命。
Each flash block has a limited number of erase cycles, and rewriting the same area would wear it out early. Wear leveling has the controller track each block's erase count and spread writes evenly across the drive to avoid premature failure of any block. Together with garbage collection, it markedly extends SSD life.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#磨损均衡 #SSD #闪存
什么是指令集架构（ISA）？
What is an instruction set architecture (ISA)?
指令集架构是软件与硬件之间的接口契约，规定了处理器能识别和执行哪些指令、寄存器如何组织、以及内存如何被访问。常见的 ISA 有 x86、ARM 和 RISC-V 等。同一种 ISA 可以由不同厂商以不同微架构实现。
An instruction set architecture is the contract between software and hardware: it specifies which instructions a processor can recognize and execute, how registers are organized, and how memory is accessed. Common ISAs include x86, ARM, and RISC-V. A single ISA can be implemented by different vendors using different microarchitectures.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#指令集 #ISA #计算机组成
32 位和 64 位系统的主要差别是什么？
What is the main difference between 32-bit and 64-bit systems?
这里的位数指 CPU 通用寄存器和地址总线的宽度。32 位系统理论上最多寻址约 4 GB 内存，64 位则可支持远超于此的地址空间，也能一次处理更宽的数据。现代操作系统和软件大多已转向 64 位以突破内存上限。
The bit count refers to the width of the CPU's general registers and address bus. A 32-bit system can theoretically address about 4 GB of memory, while 64-bit supports vastly larger address spaces and processes wider data at once. Modern OSes and software have largely moved to 64-bit to break the memory ceiling.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#位宽 #64位 #寻址
浮点数是怎么在计算机里表示的（IEEE 754）？
How are floating-point numbers represented in computers (IEEE 754)?
IEEE 754 标准把浮点数拆成符号位、指数和尾数三部分，类似科学计数法。以 32 位单精度为例：1 位符号、8 位指数、23 位尾数，通过偏移指数表达很大到很小的范围。它能表示小数，但存在精度有限和舍入误差，比较时不宜直接用等号。
The IEEE 754 standard splits a float into a sign bit, an exponent, and a mantissa, like scientific notation. In 32-bit single precision, that is 1 sign bit, 8 exponent bits, and 23 mantissa bits, with a biased exponent covering a wide range. It represents decimals but has limited precision and rounding error, so equality comparisons should avoid the equals operator.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#浮点数 #IEEE754 #表示
SRAM 和 DRAM 有什么不同？
What is the difference between SRAM and DRAM?
SRAM 用多个晶体管锁存一位数据，速度快、功耗低但面积大、成本高，常作为 CPU 缓存。DRAM 用电容存储电荷表示一位，密度高、便宜，但需要定期刷新，速度相对慢，用作主存。简单说：SRAM 快而贵，DRAM 慢而便宜量大。
SRAM stores a bit using several transistors that latch it, making it fast and low-power but large and costly, so it is used for CPU caches. DRAM stores a bit as charge in a capacitor, giving high density and low cost but requiring periodic refresh and being relatively slower, so it serves as main memory. In short, SRAM is fast and expensive, while DRAM is slower, cheaper, and high-capacity.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#SRAM #DRAM #存储
GPU 为什么比 CPU 更适合大规模并行计算？两者的设计哲学有何不同？
Why is a GPU better than a CPU at massive parallel computing? How do their design philosophies differ?
CPU 把大量芯片面积花在缓存和分支预测上，擅长少量高复杂度任务；GPU 把晶体管集中到成百上千个简单计算核上，用大规模线程并行来掩盖内存延迟。GPU 采用 SIMT 模型，同一指令作用于成组线程，通过 warp 调度换取高吞吐，因此在相同成本下并行吞吐远超 CPU。
CPUs devote a large share of die area to caches and branch prediction, excelling at a few complex tasks; GPUs concentrate transistors into hundreds of simple computing cores, hiding memory latency with massive thread parallelism. GPUs follow the SIMT model — one instruction runs across a group of threads, scheduled as warps — trading per-thread speed for high throughput, far exceeding CPU throughput at similar cost.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#GPU #并行计算 #SIMT
CPU 是什么，它在计算机中起什么作用？
What is a CPU and what role does it play in a computer?
CPU（中央处理器）是计算机的核心运算部件，负责执行程序中的指令。它通过取指、译码、执行三个基本步骤完成算术、逻辑和控制操作。可以说 CPU 是计算机的“大脑”，决定了一台机器的基本运算能力。
The CPU (Central Processing Unit) is the core computing component of a computer, responsible for executing the instructions in a program. It performs arithmetic, logic, and control operations through the basic steps of fetch, decode, and execute. Often called the computer's brain, the CPU largely determines a machine's fundamental processing power.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #中央处理器 #计算机组成
多核处理器和单核相比有什么优势？
What are the advantages of a multi-core processor over a single core?
多核处理器把多个运算核心集成在一颗芯片上，可真正同时处理多个任务或把一个任务拆成多份并行。这让计算机在运行多个程序或并行软件时更流畅，也更易在功耗受限下提升总体算力。不过只有被改写成并行形式的程序才能充分受益。
A multi-core processor integrates several computing cores on one chip, enabling genuine simultaneous handling of multiple tasks or splitting one task into parallel parts. This makes the machine smoother when running many programs or parallel software and eases raising total compute within a power budget. Only programs rewritten for parallelism fully benefit, however.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#多核 #并行 #CPU
冯·诺依曼架构的核心思想是什么？
What is the core idea of the von Neumann architecture?
冯·诺依曼架构的核心是把程序指令和数据存放在同一个存储器中，由控制单元按顺序取指执行。这种“存储程序”思想让计算机可以通过更换程序来完成不同任务。它至今仍是绝大多数计算机的基础。
The core of the von Neumann architecture is that program instructions and data are stored in the same memory, and the control unit fetches and executes them sequentially. This stored-program concept lets a computer perform different tasks simply by loading different programs. It remains the basis of most computers today.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#冯诺依曼 #存储程序 #体系结构
机械硬盘（HDD）是如何存储数据的？
How does a mechanical hard disk drive (HDD) store data?
HDD 在高速旋转的盘片上用磁性材料记录数据，磁头在盘片上移动来读写比特。由于存在机械寻道和旋转等待，它的随机访问速度较慢。优点是容量大、单位成本低、断电后数据不丢失。
An HDD records data on fast-spinning platters coated with magnetic material, and a moving head reads or writes bits on the surface. Because it involves mechanical seeking and rotational waiting, random access is slow. Its strengths are large capacity, low cost per byte, and persistence without power.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#硬盘 #HDD #存储
缓存命中与未命中分别意味着什么？
What do cache hit and cache miss mean?
当 CPU 请求的数据已经在缓存中，可直接快速取得，称为缓存命中。若不在缓存而必须去更慢的主存甚至磁盘取，称为未命中，会带来明显延迟。命中率越高，系统整体速度越接近缓存的速度。
When the data the CPU requests is already in cache and can be fetched quickly, that is a cache hit. If it is not and the CPU must go to slower main memory or even disk, that is a miss with noticeable latency. The higher the hit rate, the closer overall speed approaches the cache's speed.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#缓存命中 #缓存未命中 #性能
控制单元（CU）的作用是什么？
What is the role of the control unit (CU)?
控制单元是 CPU 的“指挥中枢”，它从内存取来指令、译码后发出一系列控制信号，指挥寄存器、ALU、内存等部件协同完成该指令。没有它，各个硬件部件就不知道何时该做什么。
The control unit is the CPU's command center: it fetches instructions from memory, decodes them, and issues control signals that direct registers, the ALU, memory, and other components to cooperate in executing each instruction. Without it, the hardware pieces would not know when to do what.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#控制单元 #CPU #指令
固态硬盘（SSD）和机械硬盘相比有什么优缺点？
What are the advantages and disadvantages of SSDs compared with HDDs?
SSD 用闪存芯片存储数据，没有机械部件，因此读写尤其是随机访问远超 HDD，也更抗震、省电。缺点是单位容量成本较高，且闪存存在写入寿命限制。为延长寿命，控制器会做磨损均衡，把写入均匀分散到各存储单元。
An SSD stores data in flash memory chips with no moving parts, so its read and especially random access speeds far exceed an HDD, and it is also shock-resistant and power-efficient. The downsides are higher cost per byte and limited write endurance of flash. To extend life, the controller performs wear leveling that spreads writes evenly across cells.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#固态硬盘 #SSD #闪存
ALU（算术逻辑单元）负责什么？
What does the ALU (arithmetic logic unit) handle?
ALU 是 CPU 中真正做计算的部分，负责对操作数执行加法、减法等算术运算以及与、或、非等逻辑运算。控制单元送来指令和数据，ALU 算出结果并返回，还会产生进位、零等状态标志供后续判断。
The ALU is the part of the CPU that actually computes: it performs arithmetic operations like addition and subtraction and logic operations like AND, OR, and NOT on its operands. The control unit supplies instructions and data, the ALU returns results, and it also produces status flags such as carry and zero for later decisions.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#ALU #运算 #CPU
什么是中断，它在计算机中起什么作用？
What is an interrupt and what role does it play in a computer?
中断是外设或程序向 CPU 发出的一种信号，要求它暂停当前工作去处理更紧急的事件，比如键盘按键或网卡来数据。CPU 收到中断后会保存现场、执行对应的中断处理程序，再恢复原工作。它让 CPU 不必反复轮询外设，提高了效率。
An interrupt is a signal from a peripheral or program asking the CPU to pause its current work and handle a more urgent event, such as a keypress or incoming network data. The CPU saves its context, runs the matching interrupt handler, then resumes. This spares the CPU from constantly polling devices and improves efficiency.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#中断 #CPU #操作系统
寄存器是什么，和内存有什么不同？
What is a register and how is it different from memory?
寄存器是 CPU 内部速度最快、容量最小的存储单元，用来临时存放正在参与运算的数据和指令地址。相比主存，寄存器离运算单元最近，访问几乎不耗时，但数量非常有限。程序运行时，数据通常先被调入寄存器再参与计算。
A register is the fastest and smallest storage unit inside the CPU, used to temporarily hold data being operated on and instruction addresses. Compared with main memory, registers sit closest to the arithmetic units and can be accessed almost instantly, but their number is very limited. During execution, data is typically loaded into registers before computation.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#寄存器 #CPU #存储
CPU 的时钟频率（GHz）代表什么？
What does a CPU's clock frequency (GHz) represent?
时钟频率表示 CPU 内部时钟每秒震荡的次数，单位是赫兹，GHz 即十亿次每秒。每个时钟周期推动流水线前进一步，频率越高通常单核吞吐越快。但它不是性能的唯一指标，核心数、架构效率同样关键。
Clock frequency is how many times per second the CPU's internal clock oscillates, measured in hertz, with GHz meaning billions of cycles per second. Each cycle advances the pipeline a step, so higher frequency usually means faster single-core throughput. It is not the only performance factor; core count and architecture efficiency matter too.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#时钟频率 #CPU #性能
计算机中的“总线”是什么？
What is a bus in a computer?
总线是计算机各部件之间传输数据、地址和控制信号的公共通道，类似一条共享公路。CPU、内存、外设都通过总线互相通信。总线的宽度和频率会影响数据传输的速率。
A bus is the shared pathway through which a computer's components transfer data, addresses, and control signals, much like a shared highway. The CPU, memory, and peripherals all communicate over buses. A bus's width and frequency affect how fast data can move.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#总线 #计算机组成 #通信
摩尔定律说的是什么？
What does Moore's Law state?
摩尔定律由戈登·摩尔提出，观察认为集成电路上可容纳的晶体管数量约每两年翻一番，带动算力持续提升、成本下降。它更像一条经验趋势而非物理定律，近年在工艺逼近原子尺度后增速已放缓。
Moore's Law, observed by Gordon Moore, holds that the number of transistors on an integrated circuit roughly doubles about every two years, driving steady gains in compute and falling costs. It is an empirical trend rather than a physical law, and its pace has slowed as fabrication nears atomic scales.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#摩尔定律 #集成电路 #趋势
内存（RAM）是干什么用的？
What is the purpose of memory (RAM)?
内存（随机存取存储器）是计算机运行时临时存放程序和数据的场所，CPU 需要的数据大多从这里快速读取。它的读写速度远快于硬盘，但断电后内容会丢失。程序启动或文件打开时，相关的内容会被加载到内存中运行。
Memory (random-access memory) is the temporary workspace where a computer holds programs and data while they run, and the CPU mostly reads what it needs from here. It is far faster than a disk but loses its contents when power is off. When you launch a program or open a file, the relevant content is loaded into RAM to execute.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#内存 #RAM #存储
位（bit）和字节（byte）是什么关系？
What is the relationship between a bit and a byte?
位（bit）是信息的最小单位，只能取 0 或 1。字节（byte）通常由 8 个位组成，是计算机存储和寻址的基本单位，可表示 0 到 255 的一个数值。文件大小、内存容量一般都按字节及其倍数（KB、MB）来计量。
A bit is the smallest unit of information, taking only 0 or 1. A byte is usually 8 bits and is the basic unit of storage and addressing, representing one value from 0 to 255. File sizes and memory capacities are generally measured in bytes and their multiples like KB and MB.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#位 #字节 #存储单位