什么是投机执行（Speculative Execution）？它和幽灵漏洞有什么关系？
What is speculative execution, and how is it linked to the Spectre vulnerability?
投机执行会提前猜着跑可能用不到的指令以提速，出错再回滚。幽灵利用这一点，让被丢弃的推测在缓存留下痕迹，从而偷到数据。
Speculative execution runs possibly unneeded instructions ahead for speed, rolling back on error. Spectre exploits it: discarded speculation leaves cache traces that leak data.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #幽灵 #安全
什么是分支预测？预测错了为什么会变慢？
What is branch prediction, and why does a wrong prediction slow things down?
分支（如 if）让 CPU 不知下一步走哪边，预测器猜测方向并提前执行。猜错就要丢弃已做的工作并重来，造成停顿。
A branch such as if makes the next path uncertain; the predictor guesses and executes ahead. A wrong guess discards that work and restarts, causing a stall.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #分支预测
什么是乱序执行（Out-of-Order Execution）？
What is out-of-order execution?
CPU 不严格按程序顺序执行指令，而是看哪些数据已就绪就先算哪些，最后再按原顺序提交结果，以隐藏等待、提升效率。
The CPU executes instructions as their data becomes ready rather than strictly in program order, then retires results in order, hiding stalls and boosting efficiency.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #乱序执行
什么是硬件预取（Prefetch）？
What is hardware prefetching?
预取器会猜测接下来要用的数据，提前从内存搬进缓存，等真正用到时已就位，减少等待。猜错则会浪费带宽。
A prefetcher predicts upcoming data and loads it into cache early, so it is ready when needed and stalls shrink. Wrong guesses waste bandwidth.
难度 专业 · 适合 小学高段(9-12)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #预取
什么是缓存一致性（Cache Coherence）？
What is cache coherence?
多核各自有缓存，若同一数据被改，其他核可能看到旧值。缓存一致性协议（如 MESI）保证多核看到的数据最终一致。
With per-core caches, one core's change could leave others seeing stale data. Coherence protocols like MESI ensure multicore views stay consistent.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#缓存 #多核
指令缓存和数据缓存（I-Cache / D-Cache）有什么区别？
What is the difference between instruction cache (I-Cache) and data cache (D-Cache)?
I-Cache 存即将执行的指令，D-Cache 存运算用的数据。分开设计可让取指令和取数据同时进行，提升并行度。
I-Cache holds instructions to execute; D-Cache holds data being computed. Splitting them lets fetching instructions and data happen in parallel.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#缓存 #指令
什么是超标量（Superscalar）和 SIMD？
What are superscalar execution and SIMD?
超标量指 CPU 一个周期能发射多条指令并行。SIMD 是一条指令同时对多个数据做同样运算（如一次加 8 个数），适合图像和音视频。
Superscalar means issuing multiple instructions per cycle. SIMD runs one instruction on many data items at once, such as adding 8 numbers together, great for media.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #SIMD #并行
什么是 CPU 的 IPC（每周期指令数）？
What is IPC (instructions per cycle) for a CPU?
IPC 表示每个时钟周期平均完成的指令数。同频率下 IPC 越高性能越强，是衡量架构效率的重要指标。
IPC is the average number of instructions completed per clock cycle. At the same frequency, higher IPC means better performance and reflects architectural efficiency.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #IPC
汇编语言是什么？今天为什么还有人学它？
What is assembly language, and why do people still learn it?
汇编是离机器码最近的人读语言，每条通常对应一条 CPU 指令。它用于嵌入式、驱动、性能极限优化和安全逆向分析。
Assembly is the human-readable form closest to machine code, roughly one line per CPU instruction. It is used in embedded systems, drivers, extreme optimization, and security analysis.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#汇编 #底层
什么是指令集架构（ISA）？x86 和 ARM 主要区别是什么？
What is an instruction set architecture (ISA), and how do x86 and ARM differ?
ISA 是 CPU 能理解的指令规范。x86 是复杂指令集（CISC），单条指令能做复杂事；ARM 是精简指令集（RISC），指令简单、功耗低，常见于手机。
An ISA is the specification of instructions a CPU understands. x86 is CISC with complex instructions, while ARM is RISC with simple, low-power instructions common in phones.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#指令集 #x86 #ARM
什么是 CPU 流水线？为什么它能让处理器更快？
What is CPU pipelining, and why does it make processors faster?
流水线把一条指令拆成取指、译码、执行等多个阶段，像工厂流水线一样让不同指令的不同阶段同时跑，提高单位时间完成的指令数。
Pipelining splits an instruction into stages such as fetch, decode, and execute, so different stages of different instructions run at once like a factory line, raising throughput.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #流水线
时钟频率（GHz）是什么？频率越高电脑一定越快吗？
What is clock frequency (GHz)? Does higher frequency always mean a faster computer?
频率表示每秒时钟脉冲次数，类似节拍。频率高通常更快，但还要看每周期能做多少事（IPC）和散热，所以不能只看 GHz。
Frequency is clock pulses per second, like a metronome. Higher is usually faster, but it also depends on work per cycle (IPC) and cooling, so GHz alone isn't everything.
难度 入门 · 适合 小学低段(6-8)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #时钟频率
为什么 CPU 需要缓存（Cache）？L1、L2、L3 有什么区别？
Why does a CPU need caches, and what are L1, L2, and L3?
内存比 CPU 慢很多，缓存用更快但更小的 SRAM 暂存常用数据。L1 最快最小、常在每个核心内；L2 次之；L3 更大、常由多核共享。
Memory is much slower than the CPU, so caches use faster but smaller SRAM to hold frequently used data. L1 is fastest and smallest per core, L2 is next, and L3 is larger and often shared across cores.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #缓存
什么是寄存器？它和内存有什么不同？
What are registers, and how do they differ from memory?
寄存器是 CPU 内部极少、极快、临时存放正在运算数据的小格子。内存大但慢，数据要先搬进寄存器才能被计算。
Registers are a tiny, ultra-fast on-CPU storage for data being computed. Memory is large but slow, so data must be loaded into registers first.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #寄存器