什么是指令集架构（如 x86、ARM）？
What is an instruction set architecture (like x86, ARM)?
指令集架构定义了 CPU 能直接执行的指令种类和格式；x86 多用于电脑、ARM 以低功耗见长，广泛用于手机和移动设备。
An instruction set architecture defines the instructions a CPU can execute directly; x86 is common in PCs while ARM, power-efficient, dominates phones and mobile devices.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#指令集 #x86 #ARM
什么是寄存器，为什么它比内存快？
What is a register and why is it faster than memory?
寄存器是 CPU 内部极小的存储单元，离运算核心最近、直接被指令访问，因此比需要多层访问的主存快得多。
A register is a tiny storage unit inside the CPU, closest to the arithmetic core and directly accessed by instructions, so it is far faster than main memory.
难度 专业 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#寄存器 #CPU #速度
什么是摩尔定律？
What is Moore's Law?
摩尔定律观察到集成电路上的晶体管数量约每两年翻一倍，使芯片性能持续提升、成本下降，但近年已逐渐放缓。
Moore's Law observed that transistor counts on chips roughly double every two years, driving performance up and cost down, though the trend has slowed recently.
难度 专业 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#摩尔定律 #芯片 #趋势
为什么显卡的显存带宽常常比显存容量更能决定实际性能？
Why does a GPU's memory bandwidth often decide real performance more than its memory capacity?
GPU 有成千上万个并行线程，其算力（每秒浮点运算次数）增长远快于显存带宽（每秒字节数），因此大量真实内核落在带宽受限区间：判据是算术强度，即每搬运一个字节做多少次浮点运算，当它低于芯片的浮点每字节比值时，速度由带宽而非算力决定。屋顶线模型把这两条限制画成一条折线，一眼就能看出内核处在带宽斜坡还是算力平台上。容量只决定模型或数据集能不能装下，装下之后再多也不会更快，这也是大模型推理格外看重 HBM 带宽、而优化手段集中在算子融合、分块与提高数据复用的原因。
A GPU runs thousands of parallel threads and its arithmetic throughput in floating-point operations per second has grown far faster than its memory bandwidth in bytes per second, so many real kernels sit in the bandwidth-bound regime: whenever arithmetic intensity — operations performed per byte moved — falls below the chip's flops-per-byte ratio, bandwidth rather than compute sets the speed. The roofline model plots both limits as one curve, making it immediately visible whether a kernel lies on the bandwidth slope or the compute ceiling. Capacity only determines whether a model or dataset fits at all, and beyond that extra gigabytes add no speed, which is why LLM inference is judged on HBM bandwidth and optimization focuses on operator fusion, tiling and data reuse.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-11-04
来源 · Source
Williams、Waterman 与 Patterson《Roofline: An Insightful Visual Performance Model for Multicore Architectures》(Communications of the ACM, 2009)；NVIDIA《CUDA C++ Programming Guide》
Williams, Waterman & Patterson, "Roofline: An Insightful Visual Performance Model for Multicore Architectures," Communications of the ACM (2009); NVIDIA, "CUDA C++ Programming Guide"
独立核验依据 · Independent verification: 核验依据 1 Crossref DOI 10.1145/1498765.1498785
#显存带宽 #算术强度 #屋顶线模型 #GPU性能
CPU 的流水线（pipeline）为什么会“停顿”（stall）？
Why does a CPU pipeline 'stall'?
流水线把一条指令拆成取指、译码、执行等多级并行推进；当后一级需要前一级还没算出的结果（数据相关）、或遇到分支误判、或硬件资源冲突时，就必须插入空泡等待，这就是停顿，会降低指令吞吐。
A pipeline splits an instruction into fetch/decode/execute stages running in parallel; when a later stage needs a result not yet ready (data hazard), a mispredicted branch occurs, or resources clash, bubbles are inserted to wait—that's a stall, lowering throughput.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#流水线 #停顿
在 FPGA 设计中，为什么跨时钟域直接传输单比特信号可能出错？两级触发器同步器如何降低亚稳态风险？
In FPGA design, why can transferring a single-bit signal directly across clock domains go wrong, and how does a two-flip-flop synchronizer reduce the metastability risk?
当输入信号在触发器的建立—保持窗口内变化时，输出可能进入既非0也非1的亚稳态，并经过不确定时间后才稳定。异步时钟之间无法保证不违反该窗口。两级同步器让第一级的亚稳态有整整一个时钟周期衰减，第二级再采样时几乎必然已恢复为确定的0或1；失效率随时间指数下降，工程师据此计算同步器的平均无故障时间来评估可靠性。
If a signal changes inside a flip-flop's setup-hold window, its output may enter metastability: an invalid voltage halfway between levels that persists for an unpredictable time before settling. Unrelated clock domains guarantee nothing about avoiding that window. A two-flip-flop synchronizer gives the first stage nearly one full clock period to decay before the second stage samples it, so recovery is overwhelmingly likely; residual failure probability decays exponentially, and engineers derive a synchronizer MTBF from this decay to quantify reliability.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 已核验 · Verified 2026-11-04
来源 · Source
Ginosar,《Fourteen ways to fool your synchronizer》,第9届异步电路与系统国际研讨会论文集（ASYNC 2003） (DOI: 10.1109/async.2003.1199169)
Ginosar, 'Fourteen ways to fool your synchronizer', Proc. 9th International Symposium on Asynchronous Circuits and Systems (ASYNC 2003), DOI: 10.1109/async.2003.1199169
独立核验依据 · Independent verification: 核验依据 1 Crossref DOI 10.1109/async.2003.1199169
#亚稳态 #跨时钟域 #同步器
为什么计算机需要内存层次结构？
Why do computers need a memory hierarchy?
寄存器、缓存、内存、磁盘在速度与容量上呈反比，层次结构用局部性原理把常用数据放在更快但更小的存储层，兼顾性能与成本。
Registers, caches, RAM and disk trade speed for capacity; the hierarchy exploits locality to keep hot data in faster, smaller tiers, balancing performance and cost.
难度 进阶 · 适合 小学高段(9-12)
CC BY 4.0 · 来源待核验 · Source pending review
来源 · Source
出处备注：此条未指向带版次的可引用著作（通识性内容、机构文件或未展开的英文书名），本库不提供独立书目出处；如需精确引用，需由编辑补全具体篇目与版次。
Patterson & Hennessy
Patterson & Hennessy
#硬件 #存储
什么是GPU，它和CPU有什么不同？
What is a GPU and how is it different from a CPU?
GPU（图形处理器）擅长同时并行处理大量简单计算，专为图像和AI训练设计；CPU 更擅长少而复杂的任务。
A GPU (graphics processing unit) excels at many simple calculations in parallel, built for graphics and AI; a CPU handles fewer, more complex tasks.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#GPU #并行 #硬件
什么是固态硬盘（SSD），它比机械硬盘快在哪？
What is an SSD and why is it faster than a mechanical hard drive?
SSD 用闪存芯片存储、没有移动部件，靠电子读写，因此比靠磁头转动找数据的机械硬盘更快也更耐震。
An SSD stores data on flash chips with no moving parts and reads electronically, so it is faster and more shock-resistant than a mechanical drive with spinning disks.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#SSD #闪存 #存储
GPU 的 SIMT 执行模型是什么？
What is the SIMT execution model of a GPU?
SIMT（单指令多线程）让成百上千个轻量线程以“线程束（warp）”为单位，同一时刻执行同一条指令但操作不同数据，非常适合矩阵乘法等高度并行的任务；但当线程走不同分支时会串行执行，拖慢整体。
SIMT (single-instruction multiple-thread) runs thousands of light threads in warps, all executing the same instruction on different data—ideal for massively parallel work like matrix multiply. Divergent branches run serially, slowing things.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#GPU #SIMT
嵌入式系统的看门狗定时器如何防止程序跑飞?实际使用中有哪些常见误区?
How does a watchdog timer keep an embedded system from running wild, and what are common mistakes when using one?
看门狗是硬件递减计数器,主流程必须周期性喂狗(重载计数值);一旦程序死锁或跑飞导致无法按时喂狗,计数器归零便触发芯片复位,让系统回到已知初始态。典型误区是把喂狗分散到多个任务或中断里——某个任务卡死后其余代码仍在喂狗,故障被掩盖;正确做法是由统一监控逻辑确认各关键任务心跳后再集中喂狗。
A watchdog is a hardware down-counter the main flow must reload periodically ('kicking'); if the program deadlocks or runs away and misses the deadline, the counter hits zero and resets the chip into a known state. A typical mistake is kicking from several tasks or interrupts: one task hangs while the rest keep feeding the timer, masking the fault — the sound pattern is a single supervisor that verifies heartbeats of all critical tasks before kicking once.
难度 进阶 · 适合 大众
CC BY 4.0 · 来源待核验 · Source pending review
来源 · Source
出处备注：著录仅给书名，无版次与年份；同一书名常对应多个版次，不臆测具体版本。
意法半导体 RM0090《STM32F4 参考手册》,第 18 章 独立看门狗(IWDG)
STMicroelectronics RM0090, STM32F4 Reference Manual, Chapter 18 'Independent watchdog (IWDG)'
#嵌入式系统 #看门狗定时器
嵌入式实时系统做可调度性分析时，为什么依据最坏情况执行时间（WCET）而不是平均执行时间？
In embedded real-time systems, why does schedulability analysis rely on worst-case execution time (WCET) rather than average execution time?
实时系统的正确性以是否满足截止期来定义，只要有一次运行超时就可能造成失效，因此分析必须覆盖所有执行路径而非典型路径。WCET 通过结合静态分析与测量上界给出可论证的时间保证；平均值会把中断、缓存扰动等长尾因素隐藏掉，用它排布调度会导致偶发超时。工程实践中通常拿 WCET 配合利用率界或响应时间分析来验证任务集可行。
Correctness in a real-time system means meeting every deadline, so analysis must bound all execution paths rather than the typical one; a single overrun can already count as failure. WCET combines static analysis with measured upper bounds to yield demonstrable timing guarantees, whereas averages hide long-tail effects like interrupts and cache perturbations that surface as sporadic misses. In practice engineers pair WCET with utilization bounds or response-time analysis to prove a task set feasible.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-11-03
来源 · Source
Glenn Reeves（JPL）《What Really Happened on Mars Rover Pathfinder》(1997)；Sha、Rajkumar 与 Lehoczky《Priority Inheritance Protocols》(IEEE Transactions on Computers, 1990)
Glenn Reeves (JPL), "What Really Happened on Mars Rover Pathfinder" (1997); Sha, Rajkumar & Lehoczky, "Priority Inheritance Protocols," IEEE Transactions on Computers (1990)
独立核验依据 · Independent verification: 核验依据 1 CROSSREF 标识 10.1109/12.57058：Priority inheritance protoc
#嵌入式系统 #WCET
FPGA 是如何用查找表（LUT）实现任意布尔组合逻辑的？为什么说一个 6 输入 LUT 能表达任何最多含六个变量的布尔函数？
How does an FPGA implement arbitrary combinational Boolean logic with lookup tables (LUTs)? Why can a single 6-input LUT represent any Boolean function of up to six variables?
LUT 本质是一小块可写存储：函数的真值表被完整装入 64（即 2 的 6 次方）个存储单元，六个输入充当地址，读出的单元内容就是该输入组合下的函数值。由于真值表穷举了任何六变量函数的全部取值，单个 LUT 必然足以覆盖；更大规模的电路由成千上万个 LUT 经可编程互连组装。与 ASIC 把门电路固化在硅片中不同，这一结构依赖配置文件加载，灵活但面积与功耗开销更高。
A LUT is essentially a small writable memory: the function's complete truth table is loaded into 64 storage cells (2 to the power of 6), the six inputs serve as the address, and the cell read at that address is the function value. Since a truth table enumerates every output of any six-variable function, one LUT always suffices; larger circuits assemble thousands of LUTs through programmable interconnect. Unlike ASICs, where gates are hard-wired in silicon, this structure exists only once configuration is loaded - flexible but costlier in area and power.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 来源待核验 · Source pending review
来源 · Source
出处备注：著录含书名，但缺版次 / 出版社 / 年份中的一部分，需编辑补全后才能做独立比对。
S. Brown、R. Francis、J. Rose 与 Z. Vranesic 合著《现场可编程门阵列》（Field-Programmable Gate Arrays），Kluwer Academic Publishers，1992 年
S. Brown, R. Francis, J. Rose, Z. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992
#FPGA #查找表 #数字设计
什么是主板，它连接了什么？
What is a motherboard and what does it connect?
主板是一块大电路板，把 CPU、内存、硬盘、显卡等部件连在一起并让它们互相通信。
A motherboard is a large circuit board that links the CPU, memory, disk, graphics card, and more, letting them communicate.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#主板 #电路 #连接
内存（RAM）和硬盘有什么区别？
What is the difference between RAM and a hard drive?
RAM 是高速但断电即失的临时工作区，硬盘是慢一些但能长期保存的存储；程序运行时数据放在 RAM 里。
RAM is fast, temporary working space that is lost without power; a hard drive is slower but keeps data long-term. Running programs use RAM.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#RAM #硬盘 #存储
RISC 和 CISC 指令集有何不同？
How do RISC and CISC instruction sets differ?
CISC 指令丰富、单条可完成复杂操作但译码复杂；RISC 指令少而规整、单周期执行、靠编译器调度，现代 x86 与 ARM 在内部都已相互借鉴对方思想。
CISC has rich complex instructions but hard decoding; RISC uses few regular single-cycle instructions scheduled by the compiler; modern x86 and ARM both borrow from each other internally.
难度 入门 · 适合 初中(12-15)
CC BY 4.0 · 来源待核验 · Source pending review
来源 · Source
出处备注：此条未指向带版次的可引用著作（通识性内容、机构文件或未展开的英文书名），本库不提供独立书目出处；如需精确引用，需由编辑补全具体篇目与版次。
Patterson & Hennessy
Patterson & Hennessy
#硬件 #指令集
电脑的"记忆"存在哪里？
Where does a computer keep its 'memory'?
电脑用内存临时记住正在做的事，用硬盘像抽屉一样长期保存文件，断电后内存会忘，硬盘不会。
A computer uses memory to remember what it is doing right now and a hard drive like a drawer to keep files long-term; memory forgets when power is off, the drive does not.
难度 入门 · 适合 小学低段(6-8)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#内存 #硬盘 #存储
什么是CPU？
What is a CPU?
CPU（中央处理器）是电脑的"大脑"，负责执行程序里的各种计算和指令。
The CPU (central processing unit) is the computer's 'brain' that carries out the calculations and instructions in programs.
难度 入门 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#CPU #处理器 #硬件
分支预测是什么，猜错了会怎样？
What is branch prediction, and what happens when it's wrong?
CPU 遇到“如果……就……”这种判断时，会提前猜走哪条路并先算起来。猜对就省时间；猜错就得把已算的部分丢掉重来，这种“清空流水线”会让程序短暂变慢。
When hitting an 'if…then…' choice, the CPU guesses the path and computes ahead. A correct guess saves time; a wrong one discards the work and restarts, briefly slowing things down—a 'pipeline flush'.
难度 入门 · 适合 小学低段(6-8)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
来源 · Source
Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#分支预测 #CPU
同样是 USB-C 接口的线，为什么有的能外接 4K 显示器，有的只能充电？
Why can some USB-C cables drive a 4K monitor while others only charge?
USB-C 只规定了插头的机械形状，能力取决于线里实际接了哪些导线以及有没有内置电子标记芯片。仅充电线可能只接了电源和两根低速数据线，缺少高速差分对，因此无法承载 DisplayPort 替代模式的视频或 USB 3.2/4 的信号，而视频与高速传输需要四对高速通道齐全。功率同理：超过 3 安或 20 伏的供电必须靠电子标记向两端声明线材额定值，没有它就只能协商到低档功率。所以选购要看线上标注的具体协议与瓦数，而不是只看接口形状。
USB-C specifies only the connector's mechanical shape; what a cable can do depends on which wires are physically present and whether it carries an e-marker chip. A charge-only cable may include just power plus two low-speed data lines and omit the high-speed differential pairs, so it cannot carry DisplayPort Alt Mode video or USB 3.2/4 signalling, both of which need all four high-speed lanes. Power works the same way: anything above 3 A or 20 V requires the e-marker to declare the cable's rating to both ends, and without it the pair negotiates down to a lower tier. Buy by the printed protocol and wattage rating rather than by the plug shape.
难度 入门 · 适合 大众
CC BY 4.0 · 来源待核验 · Source pending review
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出处备注：著录仅给书名，无版次与年份；同一书名常对应多个版次，不臆测具体版本。
USB Implementers Forum《USB Type-C Cable and Connector Specification, Revision 2.3》与《USB Power Delivery Specification, Revision 3.1》
USB Implementers Forum, "USB Type-C Cable and Connector Specification, Revision 2.3" and "USB Power Delivery Specification, Revision 3.1"
#USB-C #电子标记 #替代模式 #供电协商
缓存（cache）是什么，为什么它又快又小？
What is a cache, and why is it fast but small?
缓存是 CPU 旁边极近、极快但很贵的小存储器，用来放最近用过的数据，下次直接取就不用去慢吞吞的内存。因为它用昂贵的 SRAM 制造，所以容量做不大，只能在“快”和“大”之间取舍。
A cache is a tiny, super-fast, expensive memory next to the CPU holding recently used data, so the next fetch skips slow RAM. Built from pricey SRAM, it stays small—a trade-off between speed and size.
难度 入门 · 适合 小学低段(6-8)
CC BY 4.0 · 已核验 · Verified 2026-08-23 · 2 条独立证据
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Hennessy & Patterson,《Computer Architecture: A Quantitative Approach》第6版,Morgan Kaufmann,2017
J. L. Hennessy and D. A. Patterson, Computer Architecture, 6th ed., Morgan Kaufmann, 2017
独立核验依据 · Independent verification: 核验依据 2 OPENLIBRARY 标识 /works/OL2664271W：Computer architecture（按
#缓存 #内存