芯粒（chiplet）异构集成如何从系统层面缓解先进制程缩放的经济与技术瓶颈？
How does chiplet-based heterogeneous integration ease the economic and technical bottlenecks of advanced-process scaling at the system level?
芯粒把不同功能模块（CPU、I/O、内存、加速器）用成熟且各自最优的制程分别制造，再通过先进封装（如 2.5D 硅中介层或 3D 混合键合）互连。这种方式绕开了单颗大尺寸 SoC 在良率与光罩面积上的限制，降低了单芯片成本，并允许混用不同工艺节点与材料。
Chiplets are separately built in the most suitable, often mature process nodes for each function (CPU, I/O, memory, accelerator) and then interconnected by advanced packaging such as 2.5D silicon interposers or 3D hybrid bonding. This sidesteps reticle-size and yield limits of a single large SoC, lowers cost per die, and permits mixing of different process nodes and materials.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 来源待核验 · Source pending review
来源 · Source
出处备注：作者 / 书名 / 版次 / 出版社 / 年份齐备，仅缺独立比对证据；已在可信度报告单列披露，不再重复核验。
Lau，《芯粒设计与异构集成》（Springer, 2023）
Lau, J., 'Chiplet Design and Heterogeneous Integration' (Springer, 2023)
#芯粒 #异构集成 #先进封装 #良率
超导量子比特（如 transmon）如何通过对电荷噪声失谐来提高相干时间？
How do superconducting qubits such as the transmon improve coherence time by becoming insensitive to charge noise?
Transmon 通过增加约瑟夫森结并联的接地电容，把能级间距设计为对电荷噪声极不敏感，使工作点落在电荷不敏感区。这样单比特门的操控频率远离易出错的电荷涨落态，从而把退相干时间从早期电荷比特的纳秒级提升到百微秒量级，是目前超导量子计算机的主流方案。
The transmon adds a shunt capacitance to the Josephson junction so its level spacing becomes nearly insensitive to charge noise, placing the operating point in a charge-insensitive regime. This detunes gate operations from error-prone charge fluctuations, extending coherence from the nanosecond scale of early charge qubits to around a hundred microseconds, making it the leading superconducting qubit design.
难度 专业 · 适合 高中(15-18)
CC BY 4.0 · 来源待核验 · Source pending review
来源 · Source
出处备注：此条未指向带版次的可引用著作（通识性内容、机构文件或未展开的英文书名），本库不提供独立书目出处；如需精确引用，需由编辑补全具体篇目与版次。
Nature Physics（超导量子比特综述）
Nature Physics (superconducting qubit review)
#量子比特 #transmon #约瑟夫森结 #相干时间
高带宽内存（HBM）相比传统 DDR 内存，是通过什么方式提升带宽的？
How does high-bandwidth memory (HBM) achieve higher bandwidth than conventional DDR memory?
HBM 把多片存储裸片垂直堆叠，并通过硅通孔（TSV）和极宽的并行接口与处理器在 2.5D 中介层上紧邻互连。相比 DDR 的窄位宽长走线，HBM 以更短的距离和更宽的通道传输数据，可在较低时钟下提供远高于 DDR 的带宽并降低能耗。
HBM stacks multiple memory dies vertically and connects them to the processor through through-silicon vias (TSV) and a very wide parallel interface on a 2.5D interposer. Compared with DDR's narrow bus and long traces, HBM transfers data over a shorter distance with a much wider channel, delivering far higher bandwidth at a lower clock with less energy.
难度 进阶 · 适合 大众
CC BY 4.0 · 已核验 · Verified 2026-11-04
来源 · Source
Jun, Cho, Lee, Son,《HBM (High Bandwidth Memory) DRAM Technology and Architecture》,2017 IEEE International Memory Workshop (IMW),2017 (DOI: 10.1109/imw.2017.7939084)
Jun, Cho, Lee, Son, 'HBM (High Bandwidth Memory) DRAM Technology and Architecture', 2017 IEEE International Memory Workshop (IMW), 2017, DOI: 10.1109/imw.2017.7939084
独立核验依据 · Independent verification: 核验依据 1 Crossref DOI 10.1109/imw.2017.7939084
#高带宽内存 #硅通孔 #2.5D 封装 #带宽
当 MOSFET 尺寸持续缩小时，短沟道效应会带来哪些主要问题？
What main problems do short-channel effects cause as MOSFETs are scaled down?
沟道变短后，栅极对沟道的静电控制减弱，会出现阈值电压随沟道长度下降、漏致势垒降低（DIBL）和亚阈值斜率退化等现象。这会导致关态漏电流增大、功耗上升，并限制器件进一步缩小，是引入 FinFET、GAA 等三维结构的主要驱动力。
As the channel shortens, the gate loses electrostatic control, leading to threshold-voltage roll-off, drain-induced barrier lowering (DIBL), and degraded subthreshold slope. These raise off-state leakage and power consumption and limit further scaling, motivating 3D structures such as FinFET and GAA.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-11-03 · 2 条独立证据
来源 · Source
Streetman & Banerjee，《固态电子器件》（第7版）
Streetman & Banerjee, 'Solid State Electronic Devices' (7th ed.)
独立核验依据 · Independent verification: 核验依据 1 ISBN 9787121315657（豆瓣书目条目: 固态电子器件） · 核验依据 2 OPENLIBRARY 标识 /works/OL34943756W：Solid State Electronic
#MOSFET #短沟道效应 #阈值电压 #漏电流
硅光子技术主要解决数据中心中的什么问题？
What main problem does silicon photonics address in data centers?
随着数据流量激增，传统电互连在带宽密度和能耗上接近极限。硅光子把激光器、调制器、探测器等光学元件集成到硅芯片上，用光而非电信号在芯片间传输数据，可在更低功耗下实现每通道数十到数百 Gbps 的互连带宽。
As data traffic surges, electrical interconnects approach limits in bandwidth density and energy. Silicon photonics integrates lasers, modulators, and detectors on a silicon chip and moves data between chips with light rather than electricity, enabling tens to hundreds of Gbps per channel at much lower power.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 来源待核验 · Source pending review
来源 · Source
出处备注：此条未指向带版次的可引用著作（通识性内容、机构文件或未展开的英文书名），本库不提供独立书目出处；如需精确引用，需由编辑补全具体篇目与版次。
Nature Photonics（硅光子集成综述）
Nature Photonics (silicon photonics integration review)
#硅光子 #光互连 #数据中心 #带宽密度
鳍式场效应晶体管（FinFET）与全环绕栅极（GAA）晶体管在结构上有何主要区别？
What is the main structural difference between FinFET and gate-all-around (GAA) transistors?
FinFET 的栅极只从三面环绕竖直的鳍形沟道，而 GAA 晶体管用纳米片或纳米线作为沟道，使栅极从四周完全包裹沟道。这种全环绕结构能更强地控制沟道电流，从而更好地抑制短沟道效应，是 3 纳米及以下先进制程的主流方向。
In a FinFET the gate wraps three sides of a vertical fin-shaped channel, whereas a GAA transistor uses nanosheets or nanowires as the channel so the gate surrounds it on all four sides. The all-around gate gives stronger electrostatic control of the channel, suppressing short-channel effects more effectively, and is the mainstream choice for 3 nm and smaller process nodes.
难度 进阶 · 适合 初中(12-15)
CC BY 4.0 · 已核验 · Verified 2026-10-03
来源 · Source
S. M. Sze 与 Kwok K. Ng 著《Physics of Semiconductor Devices》（半导体器件物理）
S. M. Sze & Kwok K. Ng, Physics of Semiconductor Devices
独立核验依据 · Independent verification: 核验依据 1 ISBN 9780470068328
#晶体管 #FinFET #环绕栅极 #先进制程
RISC-V 作为一种指令集架构，相比传统商用架构最大的区别是什么？
What is the biggest difference between RISC-V and traditional commercial instruction set architectures?
RISC-V 是一个开放、免费、模块化的精简指令集，其基础指令集很小，并可通过标准扩展（如乘除法、浮点、向量）按需叠加。由于指令集规范公开，任何机构都能自由设计兼容处理器，而不必支付授权费，这降低了芯片设计的门槛。
RISC-V is an open, royalty-free, modular reduced instruction set whose base ISA is tiny and can be extended on demand with standard extensions such as multiply/divide, floating point, and vector. Because the specification is public, anyone can design compatible processors without paying license fees, lowering the barrier to chip design.
难度 进阶 · 适合 大众
CC BY 4.0 · 来源待核验 · Source pending review
来源 · Source
出处备注：著录仅给书名，无版次与年份；同一书名常对应多个版次，不臆测具体版本。
RISC-V International,《The RISC-V Instruction Set Architecture, Volume I: Base User Instruction Set》(RISC-V ISA规范)
RISC-V International, The RISC-V Instruction Set Architecture, Volume I: Base User-Instruction Set (RISC-V ISA specification)
#RISC-V #指令集 #开源 #处理器